Difference between revisions of "V4L2 FPGA/Introduction/Frame Grabber"
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| − | The frame grabber is a device that can capture single frames or a video video stream. This will be able to | + | The frame grabber is a device that can capture single frames or a video video stream. This device also enables high-speed image acquisition of high resolution images with special synchronization features in real-time. It can manage the image data load from the camera to the PC by utilizing the capabilities of the PCIe bus by using the direct memory access controller in the frame grabber which frees to CPU to perform other tasks. |
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| + | These systems are also able to perform other tasks in order to make the image available such as de-interlacing and re-formatting, it can be also capable of buffering frames and providing real time control of the device providing the frames. | ||
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| + | The developed system will be able be able to get the processed information as given by the HW accelerator and make this available to the CPU and to the user as a V4L2 device. It will also be capable of controlling the desired output format from the FPGA system. | ||
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{{V4L2_PCIe/Foot|Introduction|Introduction/Sink}} | {{V4L2_PCIe/Foot|Introduction|Introduction/Sink}} | ||
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Revision as of 13:53, 5 April 2019
 | This project is under development. |
The frame grabber is a device that can capture single frames or a video video stream. This device also enables high-speed image acquisition of high resolution images with special synchronization features in real-time. It can manage the image data load from the camera to the PC by utilizing the capabilities of the PCIe bus by using the direct memory access controller in the frame grabber which frees to CPU to perform other tasks.
These systems are also able to perform other tasks in order to make the image available such as de-interlacing and re-formatting, it can be also capable of buffering frames and providing real time control of the device providing the frames.
The developed system will be able be able to get the processed information as given by the HW accelerator and make this available to the CPU and to the user as a V4L2 device. It will also be capable of controlling the desired output format from the FPGA system.
