Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/SoM Overview"
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* Octal‐SPI NOR flash, 512Mb memory (8bit) | * Octal‐SPI NOR flash, 512Mb memory (8bit) | ||
* HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | * HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | ||
| + | |||
| + | TDA4VM and DRA829V processors architecture includes: | ||
| + | * A mix of fixed and floating-point DSP cores | ||
| + | * Arm® Cortex®-A72 cores | ||
| + | * Matrix math acceleration for machine learning | ||
| + | * Integrated ISP and vision processing acceleration | ||
| + | * 2D and 3D GPU cores | ||
| + | * H.264 encode/H.265 decode acceleration | ||
For reference on where are located these componentes, check the following image: | For reference on where are located these componentes, check the following image: | ||
Revision as of 13:03, 9 June 2021
SOM Overview
Jacinto 7 System On Module
Features
According to Texas Instruments website, Jacinto 7 SOM has the following features:
- TDA4VM/DRA829V (J721 E) processor
- Optimized power solution (PMIC)
- DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
- Octal‐SPI NOR flash, 512Mb memory (8bit)
- HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
TDA4VM and DRA829V processors architecture includes:
- A mix of fixed and floating-point DSP cores
- Arm® Cortex®-A72 cores
- Matrix math acceleration for machine learning
- Integrated ISP and vision processing acceleration
- 2D and 3D GPU cores
- H.264 encode/H.265 decode acceleration
For reference on where are located these componentes, check the following image:
Error creating thumbnail: Unable to save thumbnail to destination
Image taken from Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).
