Xilinx ZYNQ UltraScale+ MPSoC/Getting Started/ZCU 102-106

Xilinx ZYNQ UltraScale+ MPSoC
Introduction
Overview Family Developer kits
Getting Started
Xilinx Kria ZCU 102-106
Development Flows Examples
Simple Vector Addition with XRT

Xilinx provides Targeted Reference Designs (TRD) for their Evaluation Boards as a way to get started. In this case, we will explore the TRD for the ZCU106 Evaluation Board. The process for the ZCU102 should be similar to the ZCU106.

ZCU106 VCU TRD 2022.1

The Ultrascale+ EV series provide a Video Codec Unit (VCU) capable of accelerating the encoding and decoding of 4K60 video. This allows developers to combine the capabilities of the CPU, VCU, and programmable logic to achieve very high performance in multimedia applications. This version of the TRD is composed of 7 design modules:

• VCU TRD Multi-Stream Video Capture and Display
• Multi-Stream Audio Video Capture and Display
• PL DDR HDR10 HDMI Video Capture and Display
• Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display
• Xilinx Low Latency PL DDR HDMI Video Capture and Display
• Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display
• YUV444 Video Capture and Display

Download the TRD

The TRD source code, project scripts, as well as the prebuilt images can be downloaded from the following link:

ZCU106 2022.1 TRD Download

Booting the prebuilt images

The prebuilt images for each design module can be found in the images folder inside its subfolder. The steps for booting the board are as follows:

1. Insert the SD card into the host computer.
2. Format the SD card to FAT32.
3. Copy all the files inside the subfolder for the desired design module to the SD card.
4. Insert the SD card into the board.
5. Connect the power cable to the board.
6. Connect the micro-USB cable to the left micro-USB port on the board marked as UART and to the host computer.
7. Check which serial port was assigned to the Silicon Labs UART interface 0. You can do it with the following command:

dmesg | tail

You should see the following output. In this case, interface 0 (1-2:1.0) is assigned to ttyUSB0.

$ dmesg | tail
[20645.015886] usb 1-2: Manufacturer: Silicon Labs
[20645.015889] usb 1-2: SerialNumber: 17C0F7D8FD92908511E5341FA09E6DF
[20645.024393] cp210x 1-2:1.0: cp210x converter detected
[20645.025369] usb 1-2: cp210x converter now attached to ttyUSB0
[20645.025743] cp210x 1-2:1.1: cp210x converter detected
[20645.028267] usb 1-2: cp210x converter now attached to ttyUSB1
[20645.028601] cp210x 1-2:1.2: cp210x converter detected
[20645.029301] usb 1-2: cp210x converter now attached to ttyUSB2
[20645.029665] cp210x 1-2:1.3: cp210x converter detected
[20645.030418] usb 1-2: cp210x converter now attached to ttyUSB3

8. Use minicom (or an alternative) to open the serial port. You may need to install the FTDI drivers (https://ftdichip.com/drivers/vcp-drivers/).

sudo minicom -D /dev/ttyUSB0 -b 115200

9. Power on the board by using the switch next to the power connector.

Running the GStreamer application (vcu_gst_app)

First, you need to set the output resolution with the following command:

modetest -D a0070000.v_mix -s 45:3840x2160-30@BG24

Then execute the application by providing a configuration file:

vcu_gst_app <path to *.cfg file>

You can find the configuration files at /media/card/config/. For example:

root@zcu106vcutrd:~# vcu_gst_app /media/card/config/1-4kp60/Display/Single_4kp60_AVC_HIGH.cfg 
/*************************Pipeline Information Start*************************/
Pipeline Info : On
Fps Info : On
APM Info : On
Output goes on : HDMI
Frame rate : 60
Number of Source is : 1
Use case is to : Display
B Frames : 0
Bitrate : 60000
Enable L2Cache : True
Enc Name : AVC
Gop Len : 60
Profile : High
Qp Mode : Auto
Rc Mode : CBR
Num Slice : 8
GoP Mode : Basic
Filler Data : True
Low Bandwidth : False
HLG_SDR_Compatible : False
Latency Mode : Normal
GDR Mode : Disabled
Entropy Mode : CAVLC
Max Picture Size : False
Device Type : HDMI
Format : NV12
Width : 3840
Height : 2160
Relative QP : -21
Raw : False
Accelerator flag : False
Enable_scd flag : True
Enable_roi flag : False
Enable_llp2 flag : False
Src Type : Live Src

You can find more information for each design module at Zynq UltraScale+ MPSoC VCU TRD 2022.1.