Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/SoM Overview"
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| Line 47: | Line 47: | ||
|LPDDR4_IO_SEL | |LPDDR4_IO_SEL | ||
|Selects the I/O voltage level for LPDDR4: | |Selects the I/O voltage level for LPDDR4: | ||
| − | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X | + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| − | ‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
|- | |- | ||
| − | | | + | |SW1.1 |
| − | | | + | |ON |
| − | | | + | |LPDDR4_IO_SEL |
| − | | | + | |Selects the I/O voltage level for LPDDR4: |
| + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
| + | |- | ||
| + | |- | ||
| + | |SW1.1 | ||
| + | |ON | ||
| + | |LPDDR4_IO_SEL | ||
| + | |Selects the I/O voltage level for LPDDR4: | ||
| + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
| + | |- | ||
| + | |- | ||
| + | |SW1.1 | ||
| + | |ON | ||
| + | |LPDDR4_IO_SEL | ||
| + | |Selects the I/O voltage level for LPDDR4: | ||
| + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
| + | |- | ||
| + | |- | ||
| + | |SW1.1 | ||
| + | |ON | ||
| + | |LPDDR4_IO_SEL | ||
| + | |Selects the I/O voltage level for LPDDR4: | ||
| + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
| + | |- | ||
| + | |- | ||
| + | |SW1.1 | ||
| + | |ON | ||
| + | |LPDDR4_IO_SEL | ||
| + | |Selects the I/O voltage level for LPDDR4: | ||
| + | ‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 | ||
|- | |- | ||
!colspan="4"|Note: This values are average for a test time of 15 seconds. | !colspan="4"|Note: This values are average for a test time of 15 seconds. | ||
|} | |} | ||
Revision as of 13:30, 9 June 2021
SOM Overview
Jacinto 7 System On Module
Features
According to Texas Instruments website, Jacinto 7 SOM has the following features:
- TDA4VM/DRA829V (J721 E) processor
- Optimized power solution (PMIC)
- DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
- Octal‐SPI NOR flash, 512Mb memory (8bit)
- HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
Also, it is important to mention that TDA4VM and DRA829V processors heterogeneous architecture includes:
- A mix of fixed and floating-point DSP cores
- Arm® Cortex®-A72 cores
- Matrix math acceleration for machine learning
- Integrated ISP and vision processing acceleration
- 2D and 3D GPU cores
- H.264 encode/H.265 decode acceleration
Board Distribution
For reference on where are located main components and their description, check the following image:
Configuration
The switches SW1, SW2 and SW3 are called configuration switches and
| Switch Name | Default Condition | Signal | Operation |
|---|---|---|---|
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| Note: This values are average for a test time of 15 seconds. | |||
