Difference between revisions of "Xilinx ZYNQ UltraScale+ MPSoC/GStreamer/Example Pipelines/Video Decoding"
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Revision as of 12:14, 8 December 2022
 | Xilinx ZYNQ UltraScale+ MPSoC RidgeRun documentation is currently under development. |
| Xilinx ZYNQ UltraScale+ MPSoC | |
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| Introduction | |
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| Getting Started | |
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| Development Flows Examples | |
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The following pipelines were tested using the smartcam firmware, which is based on the kv260_ispMipiRx_vcu_DP Vitis platform provided by Xilinx. This platform contains the following input pipeline:
AR1335 camera -> AP1302 ISP -> MIPI CSI-2 RX Subsystem -> Video Frame Buffer WriteNetwork to display
For the sending pipeline please see the Video Encoding examples.
H.264
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H264,payload=96 ! rtph264depay ! h264parse ! omxh264dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=trueH.265
gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H265,payload=96 ! rtph265depay ! h265parse ! omxh265dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true
