Xilinx ZYNQ UltraScale+ Video Encoding using GStreamer pipelines

Xilinx ZYNQ UltraScale+ MPSoC
Introduction
Overview Family Developer kits
Getting Started
Xilinx Kria ZCU 102-106
Development Flows Examples
Simple Vector Addition with XRT

The following pipelines were tested using the smartcam firmware, which is based on the kv260_ispMipiRx_vcu_DP Vitis platform provided by Xilinx. This platform contains the following input pipeline:

AR1335 camera -> AP1302 ISP -> MIPI CSI-2 RX Subsystem -> Video Frame Buffer Write

Network to display

For the sending pipeline please see the Video Encoding examples.

H.264

gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H264,payload=96 ! rtph264depay ! h264parse ! omxh264dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true

H.265

gst-launch-1.0 udpsrc port=5000 caps=application/x-rtp,media=video,clock-rate=90000,encoding-name=H265,payload=96 ! rtph265depay ! h265parse ! omxh265dec ! kmssink driver-name=xlnx bus-id=fd4a0000.display fullscreen-overlay=true