GPIO NVIDIA Jetson Kernel Map

Introduction

This wiki page shows how to map a GPIO number with it's corresponding pad name in Tegra SoC.

GPIO Macro definition

Here is how the GPIO number is calculated based on the pad name:

• GPIO definition macro can be found at: include/dt-bindings/gpio/tegra-gpio.h

#define TEGRA_GPIO_BANK_ID_A 0
#define TEGRA_GPIO_BANK_ID_B 1
#define TEGRA_GPIO_BANK_ID_C 2
#define TEGRA_GPIO_BANK_ID_D 3
#define TEGRA_GPIO_BANK_ID_E 4
#define TEGRA_GPIO_BANK_ID_F 5
#define TEGRA_GPIO_BANK_ID_G 6
#define TEGRA_GPIO_BANK_ID_H 7
#define TEGRA_GPIO_BANK_ID_I 8
#define TEGRA_GPIO_BANK_ID_J 9
#define TEGRA_GPIO_BANK_ID_K 10
#define TEGRA_GPIO_BANK_ID_L 11
#define TEGRA_GPIO_BANK_ID_M 12
#define TEGRA_GPIO_BANK_ID_N 13
#define TEGRA_GPIO_BANK_ID_O 14
#define TEGRA_GPIO_BANK_ID_P 15
#define TEGRA_GPIO_BANK_ID_Q 16
#define TEGRA_GPIO_BANK_ID_R 17
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO_BANK_ID_T 19
#define TEGRA_GPIO_BANK_ID_U 20
#define TEGRA_GPIO_BANK_ID_V 21
#define TEGRA_GPIO_BANK_ID_W 22
#define TEGRA_GPIO_BANK_ID_X 23
#define TEGRA_GPIO_BANK_ID_Y 24
#define TEGRA_GPIO_BANK_ID_Z 25
#define TEGRA_GPIO_BANK_ID_AA 26
#define TEGRA_GPIO_BANK_ID_BB 27
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31

#define TEGRA_GPIO(bank, offset) \
	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)

Configuring gpios

Lets take pin J29 of J21 in Jetson DevKit which is labeled as GPIO19_AUD_RST (see Jetson TX1-TX2 Developer Kit Carrier Board Specification for J21 pin assignment). From the Generic Customer pinmux configuration spreadsheet privided by Nvidia one can see that its corresponding GPIO is GPIO3_PBB.03. So using the macros shown above, the gpio number would be as follows: TEGRA_GPIO(BB,3) = 27 * 8 + 3 = 219.

Here is an example configuration for the SPI interface in J21, in this case the SPI related pins are configured as Special Function and pin BB.03 as GPIO as it is used for reset:

RESET_IN -> J21 pin 29 (GPIO19_AUD_RST) -> GPIO3_PBB.03
SPI_MISO -> J21 pin 21 (SPI1_MISO)      -> GPIO3_PC.01
SPI_MOSI -> J21 pin 19 (SPI1_MOSI)      -> GPIO3_PC.00
SPI_CLK  -> J21 pin 23 (SPI_CLK)        -> GPIO3_PC.02
SPI_CS   -> J21 pin 24 (SPI1_CS0#)      -> GPIO3_PC.03

This code needs to be added to the DTB so the GPIOs are properly configured.

      chip_spi0_gpio {
        gpio-hog;
        function;
  	gpios = <
        TEGRA_GPIO(C,0) 0 // 16
        TEGRA_GPIO(C,1) 0 // 17
        TEGRA_GPIO(C,2) 0 // 18
        TEGRA_GPIO(C,3) 0 // 19
        TEGRA_GPIO(C,4) 0 // 20
        >;
        label = "SPI1_MOSI", "SPI1_MISO", "SPI_CLK", "SPI1_CS0#", "SPI1_CS1#";
        status = "okay";
      };
      chip_reset_gpio{
        gpio-hog;
        output-low;
  	gpios = <
        TEGRA_GPIO(BB,3) 0 // 219
        >;
        label = "chip-rst";
        status = "okay";
      };

RidgeRun Resources

Quick Start Client Engagement Process RidgeRun Blog Homepage Technical and Sales Support RidgeRun Online Store RidgeRun Videos Contact Us

Contact Us Visit our Main Website for the RidgeRun Products and Online Store. RidgeRun Engineering informations are available in RidgeRun Professional Services, RidgeRun Subscription Model and Client Engagement Process wiki pages. Please email to support@ridgerun.com for technical questions and contactus@ridgerun.com for other queries. Contact details for sponsoring the RidgeRun GStreamer projects are available in Sponsor Projects page.