V4L2 FPGA - Getting the Code - Running the demo

V4L2 FPGA
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Introduction
Overview Frame Grabber Sink Filtering Budget Estimator
Getting the Code
How to get the code Building and Installation Guide Running the demo
Examples
Convolutioner Pass Through Video Test Pattern Generator Xilinx OpenCV
GStreamer Pipelines
Filter Mode Frame Grabber
Supported Platforms
PicoEVB Zynq 7000 series Zynq MP-SoC series LiteFury
Contact Us

Running the demo

V4L2 FPGA includes a demo application and a demo accelerator to show a basic implementation of several Image Signal Processing (ISP) IP cores. The available demo accelerators are:

• Pass-through: a basic pass-through accelerator to see the incoming image as is.
• Convolution: applies a Laplacian Filter on the image.
• Geometric Transformation Unit: with a dynamic transformation with 3D effects.
• Histogram Equalization: a basic histogram equalization from the FPGA ISP project

The demo application has two working modes: Command Line Interface (CLI) or web, available in the port 5000. The web interface allows changing the dimensions of the image, the GStreamer pattern, and the accelerator.

Requirements

To run the demo, the platform needs to fulfill the following requirements:

• GStreamer 1.8.3 (or similar) and the bad, base, and good plug-ins. Also the development headers.
• X11-Server to launch the graphical stream
• Python 3 and Flask
• Linux kernel sources and headers (for compiling the driver)

The procedure to install the dependencies can vary depending on the platform.

Synthesizing

On the development machine (with Vivado):

1. Clone the repositories after the purchase:

# V4L2 FPGA
git clone $REPO_V4L2_FPGA_URL v4l2-fpga
cd v4l2-fpga/src/hdl/xilinx/
# FPGA ISP
git clone $REPO_FPGA_ISP_URL fpga-isp

2. Go to the root of v4l2-fpga and synthesize:

cd v4l2-fpga/

BOARD=zedboard
VENDOR=xilinx
ACCELERATOR=demo

make PLATFORM=$VENDOR EXAMPLE_BOARD=$BOARD EXAMPLE_ACCELERATOR=$ACCELERATOR EXAMPLE_MODE=SYNTHESIZE examples

This will notify where the files needed are synthesized:

• Bitstream: src/hdl/xilinx/demo/RR_Example_Bitstream_0.8.0.bit

Flash your target FPGA with this bitstream.

Compiling

On the target platform:

1. Clone the repositories after the purchase:

# V4L2 FPGA
git clone $REPO_V4L2_FPGA_URL v4l2-fpga
cd v4l2-fpga/src/hdl/xilinx/
# FPGA ISP
git clone $REPO_FPGA_ISP_URL fpga-isp

2. Go to the root of v4l2-fpga and compile:

cd v4l2-fpga/

BOARD=zedboard
VENDOR=xilinx
ACCELERATOR=demo

make PLATFORM=$VENDOR EXAMPLE_BOARD=$BOARD EXAMPLE_ACCELERATOR=$ACCELERATOR EXAMPLE_MODE=COMPILE examples

This will notify where the files needed are compiled:

• Driver: src/kernel/axi_driver/xilinx.ko or src/kernel/pci_driver/xilinx.ko, depending on your platform
• Runnable: examples/demo/runme

3. Load the driver:

sudo insmod src/kernel/axi_driver/xilinx.ko

It should create two video devices. Please, check them: ls /dev/video*

To debug: dmesg

4. Run the demo:

cd examples/demo/
./runme

You can type cli for command-line mode. It will show:

-----------------------------------------------------------------
V4L2-FPGA | FPGA-ISP - RidgeRun LLC
Demo application - CLI
-----------------------------------------------------------------
Choose an accelerator to start:
0: Pass Through
1: Convolution
2: Geometric Transformation Unit
3: Histogram Equalization
Option: 

You can type a number from 0-3 to select the accelerator.

For web, you can type web and it will start a server on the port 5000. You can access to it by http://localhost:5000.

You can select the pattern, dimensions, and accelerator. To start an accelerator, press "Start". To stop it, press "Stop".

Do you have issues?

Please, feel free to contact us in case you are having issues.

Contact support@ridgerun.com with any questions about release dates.