Difference between revisions of "Template:V4L2 FPGA/Head"
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|title={{{title|V4L2 FPGA - {{SUBPAGENAME}}}}} | |title={{{title|V4L2 FPGA - {{SUBPAGENAME}}}}} | ||
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| − | |keywords=v4l2, gstreamer acceleration, pcie, hardware acceleration, fpga | + | |keywords=v4l2, gstreamer acceleration, pcie, hardware acceleration, FPGA, gstreamer, v4l2 fpga, v4l2 driver, hardware accelerator, fpga ISP, Image Signal Processor, fpga driver, NXP, NVIDIA, i.MX8, Jetson, NVIDIA Jetson, TX1, TX2, Xavier, NVIDIA Xavier, Xilinx, Xilinx Ultrascale, Ultrascale ZCU106, Ultrascale+, PCIe interface |
|description={{{description|V4L2 FPGA is v4l2 driver which can read and write to a hardware accelerator connected through a PCIe interface.}}} | |description={{{description|V4L2 FPGA is v4l2 driver which can read and write to a hardware accelerator connected through a PCIe interface.}}} | ||
}} | }} | ||
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{| width=100% cellspacing=0 cellpadding=2 style="border: 1px solid black;" class="noprint" | {| width=100% cellspacing=0 cellpadding=2 style="border: 1px solid black;" class="noprint" | ||
Revision as of 10:45, 14 October 2021
| V4L2 FPGA |
|---|
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| Introduction |
| Getting the Code |
| Examples |
| GStreamer Pipelines |
| Supported Platforms |
| Contact Us |
