i.MX8 - IMX6vsIMX8

i.MX8
Introduction
SoC Overview Carrier Boards i.MX6 vs i.MX8
iMX8M Evaluation Kit (EVK)
Overview Getting Started Selecting Boot Mode System Setup Software Support Android_SD_Partitions_RidgeRun_Script Loading pre-built images Yocto Support Building Yocto Installing an Image Alternative image loading Android Support Building Android Installing an Image System Recovery
Nitrogen8M
Overview Getting Started Selecting Boot Mode System Setup Software Support Loading pre-built images Yocto Support Building Yocto Installing an Image Alternative image loading Customizing Boot Sequence Android Support Building Android Installing an image System Recovery
Multimedia
GPU OpenGL OpenCL OpenVX OpenVG Vulkan VPU Encoding System Decoding System ISP Support V4L2 Drivers Porting Guide GStreamer Support Package Installation Pipeline Examples Hardware-accelerated plugins RidgeRun Products GstRtspSink GstWebRTC GstPTZR GstQtOverlay
Reference Documentation
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This page presents a comparison between the i.MX6 Quad/i.MX6 Dual, i.MX7 Dual and i.MX8 Dual/i.MX8 QuadLite/i.MX8 Quad platforms, which belong to bigger families. For a more detailed information about i.MX6 and i.MX7 comparison, please refer this document. The following table is a summary of the information collected from this Applications Processors Data Sheet and the aforementioned document:

Features	i.MX6 Quad / i.MX6 Dual	i.MX7 Dual	i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad
CPU	(i.MX 6Quad) 4 x Cortex-A9 (i.MX 6Dual) 2 x Cortex-A9	Arm Cortex-A53 MPCore platform Arm Cortex-M4 core platform	2 x Cortex-A7 Cortex-M4
Maximum CPU Frequency	1.2 GHz	(A7) 1.2 GHz (M4) 200 MHz	1.5 GHz
I-Cache/D-Cache	32 KB/32 KB L1, 1 MB L2	(A7) 32 KB/32 KB L1, 512 KB L2 (M4) 16 KB/16 KB L1	Arm Cortex-A53: > Quad symmetric Cortex-A53 processors: - 32 KB L1 Instruction Cache - 32 KB L1 Data Cache - Support L1 cache RAMs protection with parity/ECC > Support of 64-bit Armv8-A architecture: - 1 MB unified L2 cache - Support L2 cache RAMs protection with ECC - Frequency of 1.5 GHz Arm Cortex-M4: - 16 KB L1 Instruction Cache - 16 KB L1 Data Cache - 256 KB tightly coupled memory (TCM)
External Memory Interface	2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L	32/16-bit LP-DDR2, DDR3, DDR3L, and LPDDR3 up to 533 MHz, rawNAND, QuadSPI NOR	32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600 8-bit NAND-Flash eMMC 5.0 Flash SPI NOR Flash QuadSPI Flash with support for XIP
Display Interface	HDMI + PHY 2 x parallel, 2 x LVDS, MIPI DSI	24-bit parallel RGB, MIPI DSI, EPDC	HDMI Display Interface: - HDMI 2.0a (1 display): up to 4096x2160 @ 60 Hz, support HDCP 2.2 and HDCP 1.4 - 20+ Audio interfaces 32-bit @ 384 kHz fs with Time Division Multiplexing (TDM) support - S/PDIF input and output - Audio Return Channel (ARC) on HDMI - Upscale HD graphics to 4K for display - Downscale 4K video to HD for display - Display Port - Embedded Display Port MIPI-DSI Display Interface: - MIPI-DSI 4 channels supporting one display, up to 1920x1080 @ 60 Hz - LCDIF display controller - Output can be LCDIF output or DC display controller output
Hardware Video Acceleration	HD (1080 + 720)p30 video decode HD 1080p30 video encode	Software Only	Video Processing Unit: - 4Kp60 HEVC/H.265 main, and main 10 decoder - 4Kp60 VP9 decoder - 4Kp30 AVC/H.264 decoder - 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder Software Only encoding support
Hardware 2D/3D Graphics Acceleration	OpenGL ES 1.1/2.0/3.0 OpenCL 1.1 EP OpenVG 1.1, 2DBLT, 4 shaders	No, but has a PxP (PiXel processing pipeline for imagine resize, rotation, overlay and color space conversion)	OpenGL/ES 3.1 Open CL 1.2 Vulkan, 4 shaders
Camera Sensor Interface (CSI)	Parallel CSI, MIPI CSI	Parallel CSI, MIPI CSI	Two MIPI-CSI2 camera inputs (4-lane each)
Universal Asynchronous Receiver/Transmitter (UART)	5	7	4
Serial Peripheral Interface (SPI)/I2C	5/3	4/4	3/4
USB Controller	1 x HS USB 2.0 OTG + PHY 1 x HS USB 2.0 Host + PHY 2 x HS USB 2.0 Host (HSIC)	2 x HS USB 2.0 OTG + PHY 1 x HS USB 2.0 Host (HSIC)	Two USB controllers and PHYs that support USB 3.0 and USB 2.0. Each USB instance contains: USB 3.0 core, which can operate in both 3.0 and 2.0 mode
Power Management	NXP MMPF0100	NXP MC32PF3000/MC34PF3000	NXP PF8100/8200
Digital Audio Interface	SSI/I2S x 3, ESAI, S/PDIF, ASRC	3 x SAI	S/PDIF input and output Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI with 8 Tx and 8 Rx channels and three SAI with 2 Tx and 2 Rx channels One SAI for 8 Tx channels for HDMI output audio One S/PDIF input for HDMI ARC input
Ethernet	1 Gbit/s + IEEE 1588	2 x Gbit w/AVB + IEEE 1588	1 GB Ethernet (IEEE1588, EEE, and AVB)
PCI Express	PCIe v2.0	PCIe v2.1	PCIe v2.0 x2 (1-lane each)
Multimedia Card (eMMC)/Secure Digital Controller (SDIO)	4 x eMMC 4.5 / SD 3.0	3 x eMMC 5.0 / SD 3.0	2x eMMC 5.0 / SD 3.0 NAND CTL (BCH62)
Security	Secure Boot, RNG, Tamper Detection, Secure Storage AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM Tamper-Resistant RTC, Secure Debug, OTP Space	ARM Trust Zone, Secure Boot, RNG, Tamper Detection, Secure Storage AES-128, AES-256, DES, 3DES, ARC4, RSA (up to 4096), ECDSA, MD5, SHA-1, SHA-224, SHA-256 32 KB Secure RAM, Tamper-Resistant RTC, Secure Debug, OTP Space	Resource Domain Controller (RDC) supports four domains and up to eight regions Arm TrustZone (TZ) architecture On-chip RAM (OCRAM) secure region protection using OCRAM controller High Assurance Boot (HAB) Cryptographic acceleration and assurance (CAAM) module Secure non-volatile storage (SNVS): Secure real-time clock (RTC) Secure JTAG controller (SJC)
Timer	3	2 x FlexTimer, 4 x GPT	3
Real-Time Clock	Secure RTC	Secure RTC	Secure RTC
Pulse Width Modulation (PWM)	4	4	4
Package	21 x 21 BGA 0.8 mm pitch	12 x 12 BGA 0.4 mm pitch 19 x 19 BGA 0.75 mm pitch	FBGA 17 x 17 mm, 0.65 mm pitch