Difference between revisions of "IMX8/IMX6vsIMX8"

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{{IMX8/Head|previous=Carrier Boards|next=Carrier Boards/iMX8MEVK|metakeywords=NXP, IMX8, Freescale, Automotive, Multimedia, IoT, advanced media processing, imx6, imx7, imx8, comparison, IMX6 vs IMX8}}
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This page presents a comparison between the i.MX6 Quad/i.MX6 Dual, i.MX7 Dual and i.MX8 Dual/i.MX8 QuadLite/i.MX8 Quad platforms, which belong to bigger families. For a more detailed information about i.MX6 and i.MX7 comparison, please refer [https://www.nxp.com/docs/en/brochure/FLYRIMXPRDCMPR.pdf this document]. The following table is a summary of the information collected from [https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQCEC.pdf this] Applications Processors Data Sheet and the aforementioned document:
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{{IMX8/Head|IMX6 vs IMX8, comparison, versus, IMX6, IMX8}}
 
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{| class="wikitable" style="margin-right: auto; margin-left: auto; border: none;"
 
{| class="wikitable" style="margin-right: auto; margin-left: auto; border: none;"
 
|-
 
|-
−
! style="background: black; color: white;" | Features!! style="background: black; color: white;" | i.MX6 Quad / i.MX6 Dual !! style="background: black; color: white;" | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad
+
! style="background: black; color: white;" | Features!! style="background: black; color: white;" | i.MX6 Quad / i.MX6 Dual !! style="background: black; color: white;" | i.MX7 Dual !! style="background: black; color: white;" | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad
 
|-
 
|-
 
! scope="row" | CPU
 
! scope="row" | CPU
−
| style="text-align: left" | <li>(i.MX 6Quad) 4 x Cortex-A9</li><li>(i.MX 6Dual) 2 x Cortex-A9<li> || style="text-align: left" | <li>Arm Cortex-A53 MPCore platform</li><li>Arm Cortex-M4 core platform</li>
+
| style="text-align: left" | <li>(i.MX 6Quad) 4 x Cortex-A9</li><li>(i.MX 6Dual) 2 x Cortex-A9<li> || style="text-align: left" | <li>Arm Cortex-A53 MPCore platform</li><li>Arm Cortex-M4 core platform</li> || style="text-align: left" | <li>2 x Cortex-A7</li><li>Cortex-M4</li>
 
|-
 
|-
 
! scope="row" | Maximum CPU Frequency
 
! scope="row" | Maximum CPU Frequency
−
| style="text-align: left" | <li>1.2 GHz</li> || style="text-align: left" | <li>1.5 GHz</li>
+
| style="text-align: left" | <li>1.2 GHz</li> || style="text-align: left" | <li>(A7) 1.2 GHz</li><li>(M4) 200 MHz</li> || style="text-align: left" | <li>1.5 GHz</li>
 
|-
 
|-
 
! scope="row" | I-Cache/D-Cache
 
! scope="row" | I-Cache/D-Cache
−
| style="text-align: left" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: left" | '''Arm Cortex-A53:'''<br><li>32 KB L1 Instruction Cache<br></li><li>32 KB L1 Data Cache<br></li><li>Support L1 cache RAMs protection with parity/ECC<br></li>'''Arm Cortex-M4:'''<br><li>16 KB L1 Instruction Cache<br></li><li>16 KB L1 Data Cache<br></li><li>256 KB tightly coupled memory (TCM)</li><br>
+
| style="text-align: left" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: left" | <li>(A7) 32 KB/32 KB L1, 512 KB L2</li><li>(M4) 16 KB/16 KB L1</li> || style="text-align: left" | <ul><li>'''Arm Cortex-A53:'''<br>'''>''' <U>Quad symmetric Cortex-A53 processors:</U><br>- 32 KB L1 Instruction Cache<br>- 32 KB L1 Data Cache<br>- Support L1 cache RAMs protection with parity/ECC<br>'''>''' <U>Support of 64-bit Armv8-A architecture:</U><br>- 1 MB unified L2 cache<br>- Support L2 cache RAMs protection with ECC<br>- Frequency of 1.5 GHz</ul></li><br><ul><li>'''Arm Cortex-M4:'''<br>- 16 KB L1 Instruction Cache<br>- 16 KB L1 Data Cache<br>- 256 KB tightly coupled memory (TCM)</ul></li><br>
 
|-
 
|-
 
! scope="row" | External Memory Interface
 
! scope="row" | External Memory Interface
−
| style="text-align: left" | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L|| style="text-align: left" | <li>32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600</li><li>8-bit NAND-Flash</li><li>eMMC 5.0 Flash</li><li>SPI NOR Flash</li><li>QuadSPI Flash with support for XIP</li>
+
| style="text-align: left" | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L || style="text-align: left" | 32/16-bit LP-DDR2, DDR3, DDR3L, and LPDDR3 up to 533 MHz, rawNAND, QuadSPI NOR || style="text-align: left" | <li>32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600</li><li>8-bit NAND-Flash</li><li>eMMC 5.0 Flash</li><li>SPI NOR Flash</li><li>QuadSPI Flash with support for XIP</li>
 
|-
 
|-
 
! scope="row" | Display Interface
 
! scope="row" | Display Interface
−
| style="text-align: left" | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: left" | '''HDMI Display Interface:'''<br>
+
| style="text-align: left" | HDMI + PHY 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: left" | 24-bit parallel RGB, MIPI DSI, EPDC || style="text-align: left" | <ul><li>'''HDMI Display Interface:'''<br>- HDMI 2.0a (1 display): up to 4096x2160 @ 60 Hz, support HDCP 2.2 and HDCP 1.4<br>- 20+ Audio interfaces 32-bit @ 384 kHz fs with Time Division Multiplexing (TDM) support<br>- S/PDIF input and output<br>- Audio Return Channel (ARC) on HDMI<br>- Upscale HD graphics to 4K for display<br>- Downscale 4K video to HD for display<br>- Display Port<br>- Embedded Display Port</ul></li><ul><li>'''MIPI-DSI Display Interface:'''<br>- MIPI-DSI 4 channels supporting one display, up to 1920x1080 @ 60 Hz<br>- LCDIF display controller<br>- Output can be LCDIF output or DC display controller output</ul></li>
−
<li>HDMI 2.0a (1 display): up to 4096x2160 @ 60 Hz,<br>support HDCP 2.2 and HDCP 1.4<br></li><li>20+ Audio interfaces 32-bit @ 384 kHz fs with Time Division Multiplexing (TDM) support<br></li><li>S/PDIF input and output<br></li><li>Audio Return Channel (ARC) on HDMI<br></li><li>Upscale HD graphics to 4K for display<br></li><li>Downscale 4K video to HD for display<br></li><li>Display Port<br></li><li>Embedded Display Port</li><br>'''MIPI-DSI Display Interface:'''<br><li>MIPI-DSI 4 channels supporting one display, up to 1920x1080 @ 60 Hz<br></li><li>LCDIF display controller<br></li><li>Output can be LCDIF output or DC display controller output</li><br>'''Audio:'''<br><li>S/PDIF input and output<br></li><li>Five synchronous audio interface (SAI) modules<br> supporting I2S, AC97, TDM, and
 
−
codec/DSP interfaces, <br>including one SAI with 16 Tx and 16 Rx channels,<br> one SAI
 
−
with 8 Tx and 8 Rx channels and <br> three SAI with 2 Tx and 2 Rx channels<br></li><li>One SAI for 8 Tx channels for HDMI output audio<br></li><li>One S/PDIF input for HDMI ARC input</li><br>
 
−
'''Camera inputs:'''<br><li>Two MIPI-CSI2 camera inputs (4-lane each)</li>
 
 
|-
 
|-
 
! scope="row" | Hardware Video Acceleration
 
! scope="row" | Hardware Video Acceleration
−
| style="text-align: left" | HD (1080 + 720)p30 video decode<br>HD 1080p30 video encode || style="text-align: left" | <li>Video Processing Unit:<br>
+
| style="text-align: left" | HD (1080 + 720)p30 video decode<br>HD 1080p30 video encode || style="text-align: left" | Software Only || style="text-align: left" | <ul><li>Video Processing Unit:<br>- 4Kp60 HEVC/H.265 main, and main 10 decoder<br>- 4Kp60 VP9 decoder<br>- 4Kp30 AVC/H.264 decoder<br>- 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder</ul></li><li>Software Only encoding support</li>
−
4Kp60 HEVC/H.265 main, and main 10 decoder<br>4Kp60 VP9 decoder<br>4Kp30 AVC/H.264 decoder<br>1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder</li>
 
 
|-
 
|-
 
! scope="row" | Hardware 2D/3D Graphics Acceleration
 
! scope="row" | Hardware 2D/3D Graphics Acceleration
−
| style="text-align: center" | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: center" | 1.5 GHz
+
| style="text-align: left" | <li>OpenGL ES 1.1/2.0/3.0</li><li>OpenCL 1.1 EP</li><li>OpenVG 1.1, 2DBLT, 4 shaders</li> || style="text-align: left" | No, but has a PxP (PiXel processing pipeline for imagine resize, rotation, overlay and color space conversion) || style="text-align: left" | <li>OpenGL/ES 3.1</li><li>Open CL 1.2</li><li>Vulkan, 4 shaders
 +
|-
 +
! scope="row" | Camera Sensor Interface (CSI)
 +
| style="text-align: left" | <li>Parallel CSI, MIPI CSI</li> || style="text-align: left" | Parallel CSI, MIPI CSI || style="text-align: left" | <li>Two MIPI-CSI2 camera inputs (4-lane each)</li>
 +
|-
 +
! scope="row" | Universal Asynchronous Receiver/Transmitter (UART)
 +
| style="text-align: left" | 5 || style="text-align: left" | 7 || style="text-align: left" | 4
 +
|-
 +
! scope="row" | Serial Peripheral Interface (SPI)/I2C
 +
| style="text-align: left" | 5/3 || style="text-align: left" | 4/4 || style="text-align: left" | 3/4
 +
|-
 +
! scope="row" | USB Controller
 +
| style="text-align: left" | <li>1 x HS USB 2.0 OTG + PHY</li><li>1 x HS USB 2.0 Host + PHY</li><li>2 x HS USB 2.0 Host (HSIC)</li> || style="text-align: left" | <li>2 x HS USB 2.0 OTG + PHY</li><li>1 x HS USB 2.0 Host (HSIC)</li> || style="text-align: left" | <li>Two USB controllers and PHYs that support USB 3.0 and USB 2.0.<br>Each USB instance contains:<br>
 +
USB 3.0 core, which can operate in both 3.0 and 2.0 mode</li>
 +
|-
 +
! scope="row" | Power Management
 +
| style="text-align: left" | <li>NXP MMPF0100</li> || style="text-align: left" | NXP MC32PF3000/MC34PF3000 || style="text-align: left" | <li>NXP PF8100/8200</li>
 +
|-
 +
! scope="row" | Digital Audio Interface
 +
| style="text-align: left" | <li>SSI/I2S x 3, ESAI, S/PDIF, ASRC</li> || style="text-align: left" | 3 x SAI || style="text-align: left" | <li>S/PDIF input and output</li><li>Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI with 8 Tx and 8 Rx channels and three SAI with 2 Tx and 2 Rx channels</li><li> One SAI for 8 Tx channels for HDMI output audio</li><li>One S/PDIF input for HDMI ARC input</li>
 +
|-
 +
! scope="row" | Ethernet
 +
| style="text-align: left" | <li>1 Gbit/s + IEEE 1588</li> || style="text-align: left" | 2 x Gbit w/AVB + IEEE 1588 || style="text-align: left" | <li>1 GB Ethernet (IEEE1588, EEE, and AVB)</li>
 +
|-
 +
! scope="row" | PCI Express
 +
| style="text-align: left" | <li>PCIe v2.0</li> || style="text-align: left" | PCIe v2.1 || style="text-align: left" | <li>PCIe v2.0 x2 (1-lane each)</li>
 +
|-
 +
! scope="row" | Multimedia Card (eMMC)/Secure Digital Controller (SDIO)
 +
| style="text-align: left" | 4 x eMMC 4.5 / SD 3.0 || style="text-align: left" | 3 x eMMC 5.0 / SD 3.0 || style="text-align: left" | 2x eMMC 5.0 / SD 3.0 NAND CTL (BCH62)
 +
|-
 +
! scope="row" | Security
 +
| style="text-align: left" | <li>Secure Boot, RNG, Tamper Detection, Secure Storage</li><li>AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM</li><li>Tamper-Resistant RTC, Secure Debug, OTP Space</li> || style="text-align: left" | <li>ARM Trust Zone, Secure Boot, RNG, Tamper Detection, Secure Storage</li><li>AES-128, AES-256, DES, 3DES, ARC4, RSA (up to 4096), ECDSA, MD5, SHA-1, SHA-224, SHA-256</li><li>32 KB Secure RAM, Tamper-Resistant RTC, Secure Debug, OTP Space</li> || style="text-align: left" | <li>Resource Domain Controller (RDC) supports four domains and up to eight regions</li><li>Arm TrustZone (TZ) architecture</li><li>On-chip RAM (OCRAM) secure region protection using OCRAM controller</li><li>High Assurance Boot (HAB)</li><li>Cryptographic acceleration and assurance (CAAM) module</li><li>Secure non-volatile storage (SNVS): Secure real-time clock (RTC)</li><li>Secure JTAG controller (SJC)</li>
 +
|-
 +
! scope="row" | Timer
 +
| style="text-align: left" | 3 || style="text-align: left" | 2 x FlexTimer, 4 x GPT || style="text-align: left" | 3
 +
|-
 +
! scope="row" | Real-Time Clock
 +
| style="text-align: left" | Secure RTC || style="text-align: left" | Secure RTC || style="text-align: left" | Secure RTC
 +
|-
 +
! scope="row" | Pulse Width Modulation (PWM)
 +
| style="text-align: left" | 4 || style="text-align: left" | 4 || style="text-align: left" | 4
 +
|-
 +
! scope="row" | Package
 +
| style="text-align: left" | 21 x 21 BGA 0.8 mm pitch || style="text-align: left" | <li>12 x 12 BGA 0.4 mm pitch</li><li>19 x 19 BGA 0.75 mm pitch</li> || style="text-align: left" | FBGA 17 x 17 mm, 0.65 mm pitch
 
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{{IMX8/Foot|Carrier_Boards/Supported_Boards|Carrier_Boards/iMX8MEVK}}
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{{IMX8/Foot|Carrier Boards|Carrier Boards/iMX8MEVK}}
 
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[[Category:iMX8]]
 
[[Category:iMX8]]

Latest revision as of 12:00, 9 March 2023


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Previous: Carrier Boards Index Next: Carrier Boards/iMX8MEVK


i.MX8
IMX8
Introduction
SoC Overview
Carrier Boards
i.MX6 vs i.MX8
iMX8M Evaluation Kit (EVK)
Overview
Getting Started
Yocto Support
Android Support
System Recovery
Nitrogen8M
Overview
Getting Started
Yocto Support
Android Support
System Recovery
Multimedia
GPU
VPU
ISP Support
GStreamer Support
RidgeRun Products
Reference Documentation
Contact Us




This page presents a comparison between the i.MX6 Quad/i.MX6 Dual, i.MX7 Dual and i.MX8 Dual/i.MX8 QuadLite/i.MX8 Quad platforms, which belong to bigger families. For a more detailed information about i.MX6 and i.MX7 comparison, please refer this document. The following table is a summary of the information collected from this Applications Processors Data Sheet and the aforementioned document:

Features i.MX6 Quad / i.MX6 Dual i.MX7 Dual i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad
CPU
  • (i.MX 6Quad) 4 x Cortex-A9
  • (i.MX 6Dual) 2 x Cortex-A9
  		•
  • Arm Cortex-A53 MPCore platform
  • Arm Cortex-M4 core platform
    		•
  • 2 x Cortex-A7
  • Cortex-M4
    • Maximum CPU Frequency
  • 1.2 GHz
    		•
  • (A7) 1.2 GHz
  • (M4) 200 MHz
    		•
  • 1.5 GHz
    • I-Cache/D-Cache 32 KB/32 KB L1, 1 MB L2
  • (A7) 32 KB/32 KB L1, 512 KB L2
  • (M4) 16 KB/16 KB L1
    		•
    • Arm Cortex-A53:
      > Quad symmetric Cortex-A53 processors:
      - 32 KB L1 Instruction Cache
      - 32 KB L1 Data Cache
      - Support L1 cache RAMs protection with parity/ECC
      > Support of 64-bit Armv8-A architecture:
      - 1 MB unified L2 cache
      - Support L2 cache RAMs protection with ECC
      - Frequency of 1.5 GHz

    • Arm Cortex-M4:
      - 16 KB L1 Instruction Cache
      - 16 KB L1 Data Cache
      - 256 KB tightly coupled memory (TCM)

    External Memory Interface 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L 32/16-bit LP-DDR2, DDR3, DDR3L, and LPDDR3 up to 533 MHz, rawNAND, QuadSPI NOR
  • 32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600
  • 8-bit NAND-Flash
  • eMMC 5.0 Flash
  • SPI NOR Flash
  • QuadSPI Flash with support for XIP
    • Display Interface HDMI + PHY 2 x parallel, 2 x LVDS, MIPI DSI 24-bit parallel RGB, MIPI DSI, EPDC
    • HDMI Display Interface:
      - HDMI 2.0a (1 display): up to 4096x2160 @ 60 Hz, support HDCP 2.2 and HDCP 1.4
      - 20+ Audio interfaces 32-bit @ 384 kHz fs with Time Division Multiplexing (TDM) support
      - S/PDIF input and output
      - Audio Return Channel (ARC) on HDMI
      - Upscale HD graphics to 4K for display
      - Downscale 4K video to HD for display
      - Display Port
      - Embedded Display Port
    • MIPI-DSI Display Interface:
      - MIPI-DSI 4 channels supporting one display, up to 1920x1080 @ 60 Hz
      - LCDIF display controller
      - Output can be LCDIF output or DC display controller output
    Hardware Video Acceleration HD (1080 + 720)p30 video decode
    HD 1080p30 video encode    		 Software Only
    • Video Processing Unit:
      - 4Kp60 HEVC/H.265 main, and main 10 decoder
      - 4Kp60 VP9 decoder
      - 4Kp30 AVC/H.264 decoder
      - 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
  • Software Only encoding support
    • Hardware 2D/3D Graphics Acceleration
  • OpenGL ES 1.1/2.0/3.0
  • OpenCL 1.1 EP
  • OpenVG 1.1, 2DBLT, 4 shaders
    		•  No, but has a PxP (PiXel processing pipeline for imagine resize, rotation, overlay and color space conversion)
  • OpenGL/ES 3.1
  • Open CL 1.2
  • Vulkan, 4 shaders
    • Camera Sensor Interface (CSI)
  • Parallel CSI, MIPI CSI
    		•  Parallel CSI, MIPI CSI
  • Two MIPI-CSI2 camera inputs (4-lane each)
    • Universal Asynchronous Receiver/Transmitter (UART) 5 7 4
    Serial Peripheral Interface (SPI)/I2C 5/3 4/4 3/4
    USB Controller
  • 1 x HS USB 2.0 OTG + PHY
  • 1 x HS USB 2.0 Host + PHY
  • 2 x HS USB 2.0 Host (HSIC)
    		•
  • 2 x HS USB 2.0 OTG + PHY
  • 1 x HS USB 2.0 Host (HSIC)
    		•
  • Two USB controllers and PHYs that support USB 3.0 and USB 2.0.
    Each USB instance contains:
    USB 3.0 core, which can operate in both 3.0 and 2.0 mode
    • Power Management
  • NXP MMPF0100
    		•  NXP MC32PF3000/MC34PF3000
  • NXP PF8100/8200
    • Digital Audio Interface
  • SSI/I2S x 3, ESAI, S/PDIF, ASRC
    		•  3 x SAI
  • S/PDIF input and output
  • Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI with 8 Tx and 8 Rx channels and three SAI with 2 Tx and 2 Rx channels
  • One SAI for 8 Tx channels for HDMI output audio
  • One S/PDIF input for HDMI ARC input
    • Ethernet
  • 1 Gbit/s + IEEE 1588
    		•  2 x Gbit w/AVB + IEEE 1588
  • 1 GB Ethernet (IEEE1588, EEE, and AVB)
    • PCI Express
  • PCIe v2.0
    		•  PCIe v2.1
  • PCIe v2.0 x2 (1-lane each)
    • Multimedia Card (eMMC)/Secure Digital Controller (SDIO) 4 x eMMC 4.5 / SD 3.0 3 x eMMC 5.0 / SD 3.0 2x eMMC 5.0 / SD 3.0 NAND CTL (BCH62)
    Security
  • Secure Boot, RNG, Tamper Detection, Secure Storage
  • AES-128, DES 3DES, ARC4, MD5, SHA-1, SHA-224, SHA-256, 16KB Secure RAM
  • Tamper-Resistant RTC, Secure Debug, OTP Space
    		•
  • ARM Trust Zone, Secure Boot, RNG, Tamper Detection, Secure Storage
  • AES-128, AES-256, DES, 3DES, ARC4, RSA (up to 4096), ECDSA, MD5, SHA-1, SHA-224, SHA-256
  • 32 KB Secure RAM, Tamper-Resistant RTC, Secure Debug, OTP Space
    		•
  • Resource Domain Controller (RDC) supports four domains and up to eight regions
  • Arm TrustZone (TZ) architecture
  • On-chip RAM (OCRAM) secure region protection using OCRAM controller
  • High Assurance Boot (HAB)
  • Cryptographic acceleration and assurance (CAAM) module
  • Secure non-volatile storage (SNVS): Secure real-time clock (RTC)
  • Secure JTAG controller (SJC)
    • Timer 3 2 x FlexTimer, 4 x GPT 3
    Real-Time Clock Secure RTC Secure RTC Secure RTC
    Pulse Width Modulation (PWM) 4 4 4
    Package 21 x 21 BGA 0.8 mm pitch
  • 12 x 12 BGA 0.4 mm pitch
  • 19 x 19 BGA 0.75 mm pitch
    		•  FBGA 17 x 17 mm, 0.65 mm pitch


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