Difference between revisions of "IMX8/IMX6vsIMX8"
< IMX8
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! scope="row" | I-Cache/D-Cache | ! scope="row" | I-Cache/D-Cache | ||
| − | | style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | <li>Arm Cortex-A53:<li><br>32 KB L1 Instruction Cache<br>32 KB L1 Data Cache<br>Support L1 cache RAMs protection with parity/ECC<br><li>Arm Cortex-M4:<li> | + | | style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | <li>Arm Cortex-A53:</li><br>32 KB L1 Instruction Cache<br>32 KB L1 Data Cache<br>Support L1 cache RAMs protection with parity/ECC<br><li>Arm Cortex-M4:</li><br>16 KB L1 Instruction Cache<br>16 KB L1 Data Cache<br>256 KB tightly coupled memory (TCM) |
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Revision as of 16:46, 7 November 2018
|
| Features | i.MX6 QuadPlus / i.MX6 DualPlus | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad |
|---|---|---|
| CPU | (i.MX 6QuadPlus) 4 x Cortex-A9 (i.MX 6DualPlus) 2 x Cortex-A9 |
Arm Cortex-A53 MPCore platform Arm Cortex-M4 core platform |
| Maximum CPU Frequency | 1.2 GHz | 1.5 GHz |
| I-Cache/D-Cache | 32 KB/32 KB L1, 1 MB L2 | 32 KB L1 Instruction Cache 32 KB L1 Data Cache Support L1 cache RAMs protection with parity/ECC 16 KB L1 Instruction Cache 16 KB L1 Data Cache 256 KB tightly coupled memory (TCM) |
