Difference between revisions of "IMX8/IMX6vsIMX8"
< IMX8
| Line 6: | Line 6: | ||
{| class="wikitable" style="margin-right: auto; margin-left: auto; border: none;" | {| class="wikitable" style="margin-right: auto; margin-left: auto; border: none;" | ||
|- | |- | ||
| − | ! style="background: black; color: white;" | Features!! style="background: black; color: white;" | i.MX6 | + | ! style="background: black; color: white;" | Features!! style="background: black; color: white;" | i.MX6 Quad / i.MX6 Dual !! style="background: black; color: white;" | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad |
|- | |- | ||
! scope="row" | CPU | ! scope="row" | CPU | ||
| − | | style="text-align: center" | (i.MX | + | | style="text-align: center" | (i.MX 6Quad) 4 x Cortex-A9<br>(i.MX 6Dual) 2 x Cortex-A9 || style="text-align: center" | Arm Cortex-A53 MPCore platform<br> Arm Cortex-M4 core platform |
|- | |- | ||
! scope="row" | Maximum CPU Frequency | ! scope="row" | Maximum CPU Frequency | ||
| Line 16: | Line 16: | ||
! scope="row" | I-Cache/D-Cache | ! scope="row" | I-Cache/D-Cache | ||
| style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | <li>Arm Cortex-A53:<br>32 KB L1 Instruction Cache<br>32 KB L1 Data Cache<br>Support L1 cache RAMs protection with parity/ECC<br></li><li>Arm Cortex-M4:<br>16 KB L1 Instruction Cache<br>16 KB L1 Data Cache<br>256 KB tightly coupled memory (TCM)</li> | | style="text-align: center" | 32 KB/32 KB L1, 1 MB L2 || style="text-align: center" | <li>Arm Cortex-A53:<br>32 KB L1 Instruction Cache<br>32 KB L1 Data Cache<br>Support L1 cache RAMs protection with parity/ECC<br></li><li>Arm Cortex-M4:<br>16 KB L1 Instruction Cache<br>16 KB L1 Data Cache<br>256 KB tightly coupled memory (TCM)</li> | ||
| + | |- | ||
| + | ! scope="row" | External Memory Interface | ||
| + | | style="text-align: center" | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L|| style="text-align: center" | 32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600<br>8-bit NAND-Flash<br>eMMC 5.0 Flash<br>SPI NOR Flash<br>QuadSPI Flash with support for XIP | ||
| + | |- | ||
| + | ! scope="row" | Display Interface | ||
| + | | style="text-align: center" | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI || style="text-align: center" | 1.5 GHz | ||
| + | |- | ||
| + | ! scope="row" | Hardware Video Acceleration | ||
| + | | style="text-align: center" | HD (1080 + 720)p30 video decode<br>HD 1080p30 video encode || style="text-align: center" | <li>Video Processing Unit:<br> | ||
| + | 4Kp60 HEVC/H.265 main, and main 10 decoder<br>4Kp60 VP9 decoder<br>4Kp30 AVC/H.264 decoder<br>1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder</li> | ||
|} | |} | ||
Revision as of 19:02, 7 November 2018
|
| Features | i.MX6 Quad / i.MX6 Dual | i.MX8M Dual / i.MX8M QuadLite / i.MX8M Quad |
|---|---|---|
| CPU | (i.MX 6Quad) 4 x Cortex-A9 (i.MX 6Dual) 2 x Cortex-A9 |
Arm Cortex-A53 MPCore platform Arm Cortex-M4 core platform |
| Maximum CPU Frequency | 1.2 GHz | 1.5 GHz |
| I-Cache/D-Cache | 32 KB/32 KB L1, 1 MB L2 | 32 KB L1 Instruction Cache 32 KB L1 Data Cache Support L1 cache RAMs protection with parity/ECC 16 KB L1 Instruction Cache 16 KB L1 Data Cache 256 KB tightly coupled memory (TCM) |
| External Memory Interface | 2 x 32 LP-DDR2, 1-ch. x 64 DDR3/DDR3L | 32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600 8-bit NAND-Flash eMMC 5.0 Flash SPI NOR Flash QuadSPI Flash with support for XIP |
| Display Interface | HDMI + PHY, 2 x parallel, 2 x LVDS, MIPI DSI | 1.5 GHz |
| Hardware Video Acceleration | HD (1080 + 720)p30 video decode HD 1080p30 video encode |
4Kp60 HEVC/H.265 main, and main 10 decoder 4Kp60 VP9 decoder 4Kp30 AVC/H.264 decoder 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder |
