FPGA Image Signal Processor - Getting the Code - Evaluating FPGA-ISP

FPGA Image Signal Processor
Introduction
FPGA ISP Accelerators/Modules
Debayer Auto White Balance Color Space Conversion Histogram Equalizer GTU Interpolators Undistort Convolution Fast Fourier Transform
Getting the Code
How to get the code Evaluating FPGA-ISP Building and Installation Guide
Examples
FFMPEG Custom Accelerator
GStreamer Pipelines
Debayer Auto White Balance Color Space Conversion Histogram Equalizer GTU Undistort
Tested Platforms
PicoEVB Zynq 7000 series Zynq MP-SoC series LiteFury
Contact us

Introduction

RidgeRun gives you the opportunity to evaluate their products, and the FPGA-ISP is not an exception. With the evaluation version, you can test our ISP modules one by one, seeing the performance and suitability of your application.

Requirements

In order to test the FPGA-ISP, you will need to have access to our V4L2-FPGA driver to access our evaluation IPs. Also, make sure you have a compatible platform. Currently, FPGA-ISP is supported by:

Embedded systems:

• NVIDIA Xavier
• i.MX8 EVK

FPGA:

• PicoEVB (Artix 7 XC7A50T CSG325 -2l)

Communication:

• 64-bit AXI-Stream (I/O data)
• AXI-Lite (Control)

Also, it is important to have Vivado installed on your host computer in order to flash the FPGA with the evaluation bitstream.

Features in the Evaluation

The following table summarizes the features available in both the professional and evaluation version of the element.

Table 1. Features provided in the evaluation version

Feature	Professional	Evaluation
Maximum framerate streaming	Y	Y
GStreamer support capability	Y	Y
Control setup	All	All
Unlimited Streaming Time	Y	N (1)
Source Code	Y	N

(1) The evaluation version will limit the streaming time of each pad to 3 minutes (at 30fps) or 5400 frames.

Request the evaluation

Please email to support@ridgerun.com for technical questions and for an evaluation version (if available).

Also, provide the following information in order to get a better idea of your requirements:

• Embedded System Platform: i.e. NVIDIA Xavier
• Framework: i.e Jetpack 4.2.1
• Operating System and Kernel version: i.e Ubuntu 16.04 (Linux nvidia-desktop 4.9.140-tegra). You can get access to this information by using uname -a
• FPGA vendor: i.e Xilinx
• FPGA carrier: i.e. PicoEVB
• FPGA model: Artix 7 XC7A50T CSG325 -2l
• Communication port: i.e PCI-e 2.0 1 lane

Flashing our evaluation IPs

The process to flash the IP into the FPGA is the same as the process followed by the Professional version. You can get more information visiting Installing FPGA Firmware.

Please, note that the described process is based on the PicoEVB. You might need to follow your FPGA instruction in case of a different FPGA.