Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/SoM Overview"
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==== Features ==== | ==== Features ==== | ||
| − | According to [https://www.ti.com/tool/J721EXSOMXEVM#description Texas Instruments website], Jacinto 7 SOM has the following features: | + | According to [https://www.ti.com/tool/J721EXSOMXEVM#description Texas Instruments website], Jacinto 7 SOM has the following key features: |
| − | * | + | * Heterogeneous processing cores: |
| + | ** Dual C66x DSP and C71x 64bit DSP | ||
| + | ** PowerVR 8XE Graphics Processing Unit (GPU) | ||
| + | * Quad ARM Cortex-R5F 1 GHz microcontrollers | ||
| + | * Dual ARM Cortex-A72 2 GHz microprocessors | ||
| + | * Key differentiated hardware acceleration for Imaging and Deep Learning: | ||
| + | ** 7th generation Vision Pre-Processing accelerator (VPAC) | ||
| + | ** Depth and Motion Perception Accelerator (DMPAC) | ||
| + | ** C71x DSP with MMA accelerator for Deep Learning acceleration | ||
| + | ** Video acceleration multi-format up to 4k60 decode and 1080p60 encode | ||
| + | * Scalable hardware and software platform with high commonality | ||
| + | * High-performance, highly-integrated, peripheral-rich processors enable key automotive applications | ||
| + | |||
| + | Highlighted hardware features are: | ||
| + | |||
| + | * C7X floating point, vector DSP, up to 1.0 GHz | ||
| + | * Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS at 1.0 GHz | ||
| + | * Vision Processing Accelerators (VPAC) with Image Signal Processing (ISP) and multiple vision assist accelerators | ||
| + | * Depth and Motion Processing Accelerators (DMPAC) | ||
* Optimized power solution (PMIC) | * Optimized power solution (PMIC) | ||
* DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC | * DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC | ||
* Octal‐SPI NOR flash, 512Mb memory (8bit) | * Octal‐SPI NOR flash, 512Mb memory (8bit) | ||
* HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | * HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | ||
| + | * Dual ARM 64-bit Cortex-A72 | ||
| + | * 6x ARM Cortex-R5F | ||
| + | * 2x C66x floating point DSP | ||
| + | * 3D GPU PowerVR Rogue 8XE GE8430 | ||
| + | * Secure boot with secure runtime support and crypto hardware accelerators | ||
| + | * 8x 2.5Gb SGMII and 2x QSGMII | ||
| + | * 4x PCI-e controllers | ||
| + | * 2x USB 3.0 dual-role (DRD) | ||
| + | ** Each port support Type-C switching | ||
| + | * 16x MCAN modules | ||
| + | * 2x CSI2.0 4Lanes RX and 1x CSI4.0 4Lanes TX | ||
| + | ** 2.5 Gbps RX throughput per lane (20 Gbps total) | ||
| + | * Video acceleration | ||
| + | ** Ultra-HD video (1x 3840x2160@60 or 2x 3840x2160@30) H.264/H.265 decode | ||
| + | ** Full-HD video (4x 1920x1080p@60 or 8x 1920x1080p@30) H.264/H.265 decode | ||
| + | ** Full-HD video (1x 1920x1080p@60 or 3x 1920x1080p@30) H.264 encode | ||
| + | * 9x I2C interfaces | ||
| + | * 3x I3C interfaces | ||
| + | * 11x UART interfaces | ||
| + | |||
| + | [[File:Am752x-top-level.png|1100x1100px|center|AM752x Top Level Diagram [1]]] Image taken from [https://www.ti.com/product/TDA4VM] | ||
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{{Review|Move everything from here to EVM Overview|CarlosR}} | {{Review|Move everything from here to EVM Overview|CarlosR}} | ||
Revision as of 11:49, 25 June 2021
 | Getting started with TI Jacinto 7 Edge AI RidgeRun documentation is currently under development. |
| Getting started with TI Jacinto 7 Edge AI | ||||||
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| Reference Documentation | ||||||
| Contact Us |
SOM Overview
Jacinto 7 System On Module
Features
According to Texas Instruments website, Jacinto 7 SOM has the following key features:
- Heterogeneous processing cores:
- Dual C66x DSP and C71x 64bit DSP
- PowerVR 8XE Graphics Processing Unit (GPU)
- Quad ARM Cortex-R5F 1 GHz microcontrollers
- Dual ARM Cortex-A72 2 GHz microprocessors
- Key differentiated hardware acceleration for Imaging and Deep Learning:
- 7th generation Vision Pre-Processing accelerator (VPAC)
- Depth and Motion Perception Accelerator (DMPAC)
- C71x DSP with MMA accelerator for Deep Learning acceleration
- Video acceleration multi-format up to 4k60 decode and 1080p60 encode
- Scalable hardware and software platform with high commonality
- High-performance, highly-integrated, peripheral-rich processors enable key automotive applications
Highlighted hardware features are:
- C7X floating point, vector DSP, up to 1.0 GHz
- Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS at 1.0 GHz
- Vision Processing Accelerators (VPAC) with Image Signal Processing (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Optimized power solution (PMIC)
- DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
- Octal‐SPI NOR flash, 512Mb memory (8bit)
- HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
- Dual ARM 64-bit Cortex-A72
- 6x ARM Cortex-R5F
- 2x C66x floating point DSP
- 3D GPU PowerVR Rogue 8XE GE8430
- Secure boot with secure runtime support and crypto hardware accelerators
- 8x 2.5Gb SGMII and 2x QSGMII
- 4x PCI-e controllers
- 2x USB 3.0 dual-role (DRD)
- Each port support Type-C switching
- 16x MCAN modules
- 2x CSI2.0 4Lanes RX and 1x CSI4.0 4Lanes TX
- 2.5 Gbps RX throughput per lane (20 Gbps total)
- Video acceleration
- Ultra-HD video (1x 3840x2160@60 or 2x 3840x2160@30) H.264/H.265 decode
- Full-HD video (4x 1920x1080p@60 or 8x 1920x1080p@30) H.264/H.265 decode
- Full-HD video (1x 1920x1080p@60 or 3x 1920x1080p@30) H.264 encode
- 9x I2C interfaces
- 3x I3C interfaces
- 11x UART interfaces
Error creating thumbnail: Unable to save thumbnail to destination
 | CarlosR: Move everything from here to EVM Overview (please remove this box when addressed) |
Board Distribution
For reference on where are located the main components and their description, check the following image:
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Image taken from Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).
Configuration
The switches SW1, SW2 and SW3 are called configuration switches. Depending on how this switches are set, the system on module can fulfill different functions, check the next table:
| Switch Name | Default Condition | Signal | Operation |
|---|---|---|---|
| SW1.1 | ON | LPDDR4_IO_SEL | Selects the I/O voltage level for LPDDR4:
‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4 |
| SW1.2 | OFF | SEL_SOC_I2Cn | MUX to select I2C Interface for PMICs:
‘0’ (OFF) = PMIC I2C to SoC WKUP interface, ‘1’ (ON) = PMIC I2C to External Header (test mode only) |
| SW2.1 | OFF | SEL_GPIO8_ALT | Selection for PMIC Watchdog Timer/GPIO8:
‘0’ (OFF) = PMIC watchdog timer control is set with SW2.2, ‘1’ (ON) = PMIC I/O used for GPIO8 (test point) |
| SW2.2 | ON | LEOA_WDOG_DIS | Enable/Disable selection for PMIC Watchdog Timer:
‘0’ (OFF) = PMIC watchdog timer is enabled, ‘1’ (ON) = PMIC watchdog timer is disabled (requires SW2.1 to be set to OFF) |
| SW3.1 | ON | SOC_SAFETY_ERRz | Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC:
‘0’ (OFF) = SOC_SAFETY_ERRz (Main) is isolated from PMIC, ‘1’ (ON) = SOC_SAFETY_ERRz (Main) is connected to PMIC |
| SW3.2 | OFF | SOC_PWR_EN | Manual method of enabling PMIC:
‘0’ (OFF) = PMIC enabled by EVM system, ‘1’ (ON) = PMIC enabled manually (test mode only) |
| Note: This table is a simple rework from J721E SOM configuration switches table, located in Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A). | |||
