Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/EVM Overview"

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[[File:Emv switches3.jpg|frameless|center|600px]]
 
[[File:Emv switches3.jpg|frameless|center|600px]]
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====  Board Distribution ====
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For reference on where are located the main components and their description, check the following image:
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[[File:J7 som components2.png|1000px|frame|center|Image taken from [https://www.ti.com/lit/ug/spruis4a/spruis4a.pdf?ts=1620938339053&ref_url=https%253A%252F%252Fwww.google.com%252F Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).]]]
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==== Configuration ====
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The switches SW1, SW2 and SW3 are called configuration switches. Depending on how this switches are set, the system on module can fulfill different functions, check the next table:
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<br>
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<br>
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{| class="wikitable" style="margin: auto; text-align:center; vertical-align:middle;"
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|-
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!|Switch Name
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!|Default Condition
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!|Signal
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!|Operation
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|-
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|SW1.1
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|ON
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|LPDDR4_IO_SEL
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|Selects the I/O voltage level for LPDDR4:
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‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4
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|-
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|SW1.2
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|OFF
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|SEL_SOC_I2Cn
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|MUX to select I2C Interface for PMICs:
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‘0’ (OFF) = PMIC I2C to SoC WKUP interface, ‘1’ (ON) = PMIC I2C to External Header (test mode only)
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|-
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|-
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|SW2.1
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|OFF
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|SEL_GPIO8_ALT
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|Selection for PMIC Watchdog Timer/GPIO8:
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‘0’ (OFF) = PMIC watchdog timer control is set with SW2.2, ‘1’ (ON) = PMIC I/O used for GPIO8 (test point)
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|-
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|-
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|SW2.2
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|ON
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|LEOA_WDOG_DIS
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|Enable/Disable selection for PMIC Watchdog Timer:
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‘0’ (OFF) = PMIC watchdog timer is enabled, ‘1’ (ON) = PMIC watchdog timer is disabled
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(requires SW2.1 to be set to OFF)
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|-
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|-
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|SW3.1
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|ON
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|SOC_SAFETY_ERRz
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|Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC:
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‘0’ (OFF) = SOC_SAFETY_ERRz (Main) is isolated from PMIC, ‘1’ (ON) = SOC_SAFETY_ERRz (Main) is connected to PMIC
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|-
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|-
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|SW3.2
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|OFF
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|SOC_PWR_EN
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|Manual method of enabling PMIC:
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‘0’ (OFF) = PMIC enabled by EVM system, ‘1’ (ON) = PMIC enabled manually (test mode only)
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|-
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!colspan="4"|Note: This table is a simple rework from J721E SOM configuration switches table, located in [https://www.ti.com/lit/ug/spruis4a/spruis4a.pdf?ts=1620938339053&ref_url=https%253A%252F%252Fwww.google.com%252F Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).]
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|}
  
 
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{{Getting started with TI Jacinto 7 Edge AI/Foot|Introduction/SoM_Overview|Introduction/Getting Started}}
 
{{Getting started with TI Jacinto 7 Edge AI/Foot|Introduction/SoM_Overview|Introduction/Getting Started}}
 
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</noinclude>

Revision as of 12:46, 25 June 2021




Previous: Introduction/SoM_Overview Index Next: Introduction/Getting Started


Getting started with
TI Jacinto 7 Edge AI
Texas Instruments
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Introduction
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Demos
C++ Demos
Python Demos
RidgeRun Demos
Reference Documentation
Contact Us




The EVM setup

Requirements:

  • TDA4VM/J7ES EVM
  • 12 V power supply
  • Ethernet cable
  • UART cable
  • Minimum 16GB high-performance SD card
  • USB camera
  • Full HD eDP display

The EVM connections

Evm connections1.jpg

Boot mode switches

In order to allow the EVM to boot, please follow this switches configuration:

Emv switches3.jpg

Board Distribution

For reference on where are located the main components and their description, check the following image:

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Image taken from Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).

Configuration

The switches SW1, SW2 and SW3 are called configuration switches. Depending on how this switches are set, the system on module can fulfill different functions, check the next table:



Switch Name Default Condition Signal Operation
SW1.1 ON LPDDR4_IO_SEL Selects the I/O voltage level for LPDDR4:

‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4

SW1.2 OFF SEL_SOC_I2Cn MUX to select I2C Interface for PMICs:

‘0’ (OFF) = PMIC I2C to SoC WKUP interface, ‘1’ (ON) = PMIC I2C to External Header (test mode only)

SW2.1 OFF SEL_GPIO8_ALT Selection for PMIC Watchdog Timer/GPIO8:

‘0’ (OFF) = PMIC watchdog timer control is set with SW2.2, ‘1’ (ON) = PMIC I/O used for GPIO8 (test point)

SW2.2 ON LEOA_WDOG_DIS Enable/Disable selection for PMIC Watchdog Timer:

‘0’ (OFF) = PMIC watchdog timer is enabled, ‘1’ (ON) = PMIC watchdog timer is disabled (requires SW2.1 to be set to OFF)

SW3.1 ON SOC_SAFETY_ERRz Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC:

‘0’ (OFF) = SOC_SAFETY_ERRz (Main) is isolated from PMIC, ‘1’ (ON) = SOC_SAFETY_ERRz (Main) is connected to PMIC

SW3.2 OFF SOC_PWR_EN Manual method of enabling PMIC:

‘0’ (OFF) = PMIC enabled by EVM system, ‘1’ (ON) = PMIC enabled manually (test mode only)

Note: This table is a simple rework from J721E SOM configuration switches table, located in Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).


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