Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/SoM Overview"

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== SOM Overview ==
 
== SOM Overview ==
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  <div>
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{|class=wikitable
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    <p style="font-size: 1.7em; margin-bottom:0">Jacinto 7 System On Module</p>
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| style="background-color:#cc0000;color:#ffffff;font-size: 1.7em; height:70px; width:1900px; text-align:left; padding-left: 0px;padding-top: 0px;padding-bottom: 0px;" | [[File:Ti logo 6.png|frameless|70px]]  SoM Overview
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==== Key Features ====
 
==== Key Features ====
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<center>Image taken from [https://www.ti.com/product/TDA4VM https://www.ti.com/product/TDA4VM]
 
<center>Image taken from [https://www.ti.com/product/TDA4VM https://www.ti.com/product/TDA4VM]
  
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{{Review|Move everything from here to EVM Overview|CarlosR}}
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==== Board Distribution ====
 
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For reference on where are located the main components and their description, check the following image:
 
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[[File:J7 som components2.png|1000px|frame|center|Image taken from [https://www.ti.com/lit/ug/spruis4a/spruis4a.pdf?ts=1620938339053&ref_url=https%253A%252F%252Fwww.google.com%252F Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).]]]
 
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==== Configuration ====
 
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The switches SW1, SW2 and SW3 are called configuration switches. Depending on how this switches are set, the system on module can fulfill different functions, check the next table:
 
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<br>
 
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<br>
 
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{| class="wikitable" style="margin: auto; text-align:center; vertical-align:middle;"
 
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|-
 
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!|Switch Name
 
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!|Default Condition
 
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!|Signal
 
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!|Operation
 
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|-
 
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|SW1.1
 
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|ON
 
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|LPDDR4_IO_SEL
 
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|Selects the I/O voltage level for LPDDR4:
 
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‘0’ (OFF) = Selects 0.6 V I/O for LPDDR4X,‘1’ (ON) = Selects 1.1 V I/O for LPDDR4
 
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|-
 
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|SW1.2
 
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|OFF
 
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|SEL_SOC_I2Cn
 
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|MUX to select I2C Interface for PMICs:
 
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‘0’ (OFF) = PMIC I2C to SoC WKUP interface, ‘1’ (ON) = PMIC I2C to External Header (test mode only)
 
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|-
 
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|-
 
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|SW2.1
 
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|OFF
 
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|SEL_GPIO8_ALT
 
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|Selection for PMIC Watchdog Timer/GPIO8:
 
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‘0’ (OFF) = PMIC watchdog timer control is set with SW2.2, ‘1’ (ON) = PMIC I/O used for GPIO8 (test point)
 
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|-
 
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|-
 
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|SW2.2
 
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|ON
 
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|LEOA_WDOG_DIS
 
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|Enable/Disable selection for PMIC Watchdog Timer:
 
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‘0’ (OFF) = PMIC watchdog timer is enabled, ‘1’ (ON) = PMIC watchdog timer is disabled
 
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(requires SW2.1 to be set to OFF)
 
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|-
 
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|-
 
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|SW3.1
 
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|ON
 
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|SOC_SAFETY_ERRz
 
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|Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC:
 
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‘0’ (OFF) = SOC_SAFETY_ERRz (Main) is isolated from PMIC, ‘1’ (ON) = SOC_SAFETY_ERRz (Main) is connected to PMIC
 
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|-
 
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|-
 
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|SW3.2
 
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|OFF
 
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|SOC_PWR_EN
 
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|Manual method of enabling PMIC:
 
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‘0’ (OFF) = PMIC enabled by EVM system, ‘1’ (ON) = PMIC enabled manually (test mode only)
 
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|-
 
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!colspan="4"|Note: This table is a simple rework from J721E SOM configuration switches table, located in [https://www.ti.com/lit/ug/spruis4a/spruis4a.pdf?ts=1620938339053&ref_url=https%253A%252F%252Fwww.google.com%252F Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A).]
 
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Latest revision as of 13:24, 8 March 2023




Previous: Introduction Index Next: Introduction/EVM Overview


Getting started with
TI Jacinto 7 Edge AI
Texas Instruments
Ridgerun-logo.svg
Introduction
GStreamer
Demos
C++ Demos
Python Demos
RidgeRun Demos
Reference Documentation
Contact Us




SOM Overview

Ti logo 6.png SoM Overview

Key Features

According to Texas Instruments website, Jacinto 7 SOM has the following key features:

  • Heterogeneous processing cores:​​
    • Dual C66x DSP and C71x 64bit DSP
    • PowerVR 8XE Graphics Processing Unit (GPU)
  • Quad ARM Cortex-R5F 1 GHz microcontrollers
  • Dual ARM Cortex-A72 2 GHz microprocessors​
  • Key differentiated hardware acceleration for Imaging and Deep Learning:​
    • 7th generation Vision Pre-Processing accelerator (VPAC)​
    • Depth and Motion Perception Accelerator (DMPAC)
    • C71x DSP with MMA accelerator for Deep Learning acceleration
    • Video acceleration multi-format up to 4k60 decode and 1080p60 encode
  • Scalable hardware and software platform with high commonality
  • High-performance, highly-integrated, peripheral-rich processors enable key automotive applications

Hardware features

Highlighted hardware features are:

  • C7X floating point, vector DSP, up to 1.0 GHz
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processing (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Optimized power solution (PMIC)
  • DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
  • Octal‐SPI NOR flash, 512Mb memory (8bit)
  • HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
  • Dual ARM 64-bit Cortex-A72
  • 6x ARM Cortex-R5F
  • 2x C66x floating point DSP
  • 3D GPU PowerVR Rogue 8XE GE8430
  • Secure boot with secure runtime support and crypto hardware accelerators
  • 8x 2.5Gb SGMII and 2x QSGMII
  • 4x PCI-e controllers
  • 2x USB 3.0 dual-role (DRD)
    • Each port support Type-C switching
  • 16x MCAN modules
  • 2x CSI2.0 4Lanes RX and 1x CSI4.0 4Lanes TX
    • 2.5 Gbps RX throughput per lane (20 Gbps total)
  • Video acceleration
    • Ultra-HD video (1x 3840x2160@60 or 2x 3840x2160@30) H.264/H.265 decode
    • Full-HD video (4x 1920x1080p@60 or 8x 1920x1080p@30) H.264/H.265 decode
    • Full-HD video (1x 1920x1080p@60 or 3x 1920x1080p@30) H.264 encode
  • 9x I2C interfaces
  • 3x I3C interfaces
  • 11x UART interfaces


Error creating thumbnail: Unable to save thumbnail to destination
Image taken from https://www.ti.com/product/TDA4VM


Previous: Introduction Index Next: Introduction/EVM Overview



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