Difference between revisions of "Getting started with TI Jacinto 7 Edge AI/Introduction/SoM Overview"
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− | {{Getting started with TI Jacinto 7 Edge AI/Head|next= | + | {{Getting started with TI Jacinto 7 Edge AI/Head|next=Introduction/EVM Overview|previous=Introduction|metakeywords=}} |
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== SOM Overview == | == SOM Overview == | ||
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− | ==== Features ==== | + | {|class=wikitable |
+ | | style="background-color:#cc0000;color:#ffffff;font-size: 1.7em; height:70px; width:1900px; text-align:left; padding-left: 0px;padding-top: 0px;padding-bottom: 0px;" | [[File:Ti logo 6.png|frameless|70px]] SoM Overview | ||
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+ | ==== Key Features ==== | ||
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+ | According to [https://www.ti.com/tool/J721EXSOMXEVM#description Texas Instruments website], Jacinto 7 SOM has the following key features: | ||
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+ | * Heterogeneous processing cores: | ||
+ | ** Dual C66x DSP and C71x 64bit DSP | ||
+ | ** PowerVR 8XE Graphics Processing Unit (GPU) | ||
+ | * Quad ARM Cortex-R5F 1 GHz microcontrollers | ||
+ | * Dual ARM Cortex-A72 2 GHz microprocessors | ||
+ | * Key differentiated hardware acceleration for Imaging and Deep Learning: | ||
+ | ** 7th generation Vision Pre-Processing accelerator (VPAC) | ||
+ | ** Depth and Motion Perception Accelerator (DMPAC) | ||
+ | ** C71x DSP with MMA accelerator for Deep Learning acceleration | ||
+ | ** Video acceleration multi-format up to 4k60 decode and 1080p60 encode | ||
+ | * Scalable hardware and software platform with high commonality | ||
+ | * High-performance, highly-integrated, peripheral-rich processors enable key automotive applications | ||
+ | |||
+ | ==== Hardware features ==== | ||
− | + | Highlighted hardware features are: | |
− | * | + | * C7X floating point, vector DSP, up to 1.0 GHz |
+ | * Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS at 1.0 GHz | ||
+ | * Vision Processing Accelerators (VPAC) with Image Signal Processing (ISP) and multiple vision assist accelerators | ||
+ | * Depth and Motion Processing Accelerators (DMPAC) | ||
* Optimized power solution (PMIC) | * Optimized power solution (PMIC) | ||
* DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC | * DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC | ||
* Octal‐SPI NOR flash, 512Mb memory (8bit) | * Octal‐SPI NOR flash, 512Mb memory (8bit) | ||
* HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | * HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM | ||
+ | * Dual ARM 64-bit Cortex-A72 | ||
+ | * 6x ARM Cortex-R5F | ||
+ | * 2x C66x floating point DSP | ||
+ | * 3D GPU PowerVR Rogue 8XE GE8430 | ||
+ | * Secure boot with secure runtime support and crypto hardware accelerators | ||
+ | * 8x 2.5Gb SGMII and 2x QSGMII | ||
+ | * 4x PCI-e controllers | ||
+ | * 2x USB 3.0 dual-role (DRD) | ||
+ | ** Each port support Type-C switching | ||
+ | * 16x MCAN modules | ||
+ | * 2x CSI2.0 4Lanes RX and 1x CSI4.0 4Lanes TX | ||
+ | ** 2.5 Gbps RX throughput per lane (20 Gbps total) | ||
+ | * Video acceleration | ||
+ | ** Ultra-HD video (1x 3840x2160@60 or 2x 3840x2160@30) H.264/H.265 decode | ||
+ | ** Full-HD video (4x 1920x1080p@60 or 8x 1920x1080p@30) H.264/H.265 decode | ||
+ | ** Full-HD video (1x 1920x1080p@60 or 3x 1920x1080p@30) H.264 encode | ||
+ | * 9x I2C interfaces | ||
+ | * 3x I3C interfaces | ||
+ | * 11x UART interfaces | ||
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− | + | [[File:Am752x-top-level.png|1100x1100px|center]] | |
+ | <center>Image taken from [https://www.ti.com/product/TDA4VM https://www.ti.com/product/TDA4VM] | ||
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− | + | {{Getting started with TI Jacinto 7 Edge AI/Foot|Introduction|Introduction/EVM Overview}} | |
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Latest revision as of 13:24, 8 March 2023
Getting started with TI Jacinto 7 Edge AI RidgeRun documentation is currently under development. |
Getting started with TI Jacinto 7 Edge AI | ||||||
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Introduction | ||||||
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GStreamer | ||||||
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Demos | ||||||
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Reference Documentation | ||||||
Contact Us |
SOM Overview
SoM Overview |
Key Features
According to Texas Instruments website, Jacinto 7 SOM has the following key features:
- Heterogeneous processing cores:
- Dual C66x DSP and C71x 64bit DSP
- PowerVR 8XE Graphics Processing Unit (GPU)
- Quad ARM Cortex-R5F 1 GHz microcontrollers
- Dual ARM Cortex-A72 2 GHz microprocessors
- Key differentiated hardware acceleration for Imaging and Deep Learning:
- 7th generation Vision Pre-Processing accelerator (VPAC)
- Depth and Motion Perception Accelerator (DMPAC)
- C71x DSP with MMA accelerator for Deep Learning acceleration
- Video acceleration multi-format up to 4k60 decode and 1080p60 encode
- Scalable hardware and software platform with high commonality
- High-performance, highly-integrated, peripheral-rich processors enable key automotive applications
Hardware features
Highlighted hardware features are:
- C7X floating point, vector DSP, up to 1.0 GHz
- Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS at 1.0 GHz
- Vision Processing Accelerators (VPAC) with Image Signal Processing (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Optimized power solution (PMIC)
- DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
- Octal‐SPI NOR flash, 512Mb memory (8bit)
- HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
- Dual ARM 64-bit Cortex-A72
- 6x ARM Cortex-R5F
- 2x C66x floating point DSP
- 3D GPU PowerVR Rogue 8XE GE8430
- Secure boot with secure runtime support and crypto hardware accelerators
- 8x 2.5Gb SGMII and 2x QSGMII
- 4x PCI-e controllers
- 2x USB 3.0 dual-role (DRD)
- Each port support Type-C switching
- 16x MCAN modules
- 2x CSI2.0 4Lanes RX and 1x CSI4.0 4Lanes TX
- 2.5 Gbps RX throughput per lane (20 Gbps total)
- Video acceleration
- Ultra-HD video (1x 3840x2160@60 or 2x 3840x2160@30) H.264/H.265 decode
- Full-HD video (4x 1920x1080p@60 or 8x 1920x1080p@30) H.264/H.265 decode
- Full-HD video (1x 1920x1080p@60 or 3x 1920x1080p@30) H.264 encode
- 9x I2C interfaces
- 3x I3C interfaces
- 11x UART interfaces
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